Arithmetic processor for programmable controller

Abstract

PURPOSE: To obtain the arithmetic processor of a programmable controller whose cost performance is high by decreasing the cost of a used memory, and executing the architecture of the arithmetic processor by which a pipe line execution with the high efficiency of an application command can be attained. CONSTITUTION: An arithmetic processor 1 is constituted of an instruction fetching unit part 2, control unit 3, bit processing unit part 4, multibit processing unit part 5, and data memory bus interface part 6. The pipe line execution of a frequently-used sequence command is operated by the bit processing unit part 4, and the pipe line execution of the application command for a data processing is operated by the multibit processing unit 5 after complied to an RISC type data processing command. COPYRIGHT: (C)1992,JPO&Japio

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Cited By (3)

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    US-6950923-B2September 27, 2005Sun Microsystems, Inc.Method frame storage using multiple memory circuits
    US-6961843-B2November 01, 2005Sun Microsystems, Inc.Method frame storage using multiple memory circuits
    WO-2005015386-A1February 17, 2005Matsushita Electric Industrial Co., Ltd.プロセッサ集積回路及びプロセッサ集積回路を用いた製品開発方法